In the fabrication of integrated circuit ("IC") devices, automatic test systems ("ATS") play a vital role in ensuring that the fabricated IC devices perform according to their functional specifications. By programming the ATS to provide the devices with a simulated operating environment, the capabilities of the devices can be detected and thereafter improved. With the proliferation of very-large-scale-integration (VLSI) devices, ATSs capable of handling 100 to 200 input/output pins become a requisite link in the fabrication process of IC devices.
FIG. 1 illustrates the functional components of a typical ATS. A test engineer interacts with the ATS through user interface and test controller 160. Initially input data patterns are stored in pattern storage 100, which is essentially a data memory device. The input data patterns from pattern storage 100 are driven to the device-under-test ("DUT") 130 through drive response formatting 110 and test head 120. Drive response formatting 110 controls the timing of the input signal from input data patterns, e.g. when an input signal turns high or low, etc. Test head 120 provides interface with DUT 130 and detects output signal levels from DUT 130. Analog unit 150 is a parametric measuring unit and supplies power to DUT 130 through test head 120. Analog unit 150 also supplies references for test head 120 to interface with DUT 130. Control unit 140 is typically a high speed controller capable of providing looping, changing, and sequencing operations for the input data patterns.
The function of drive response formatting 110 is to provide fine controls of marker placement in the ATS. The control of marker placement involves such parameters as pulse width, edge placements between data and clock, and precise time for evaluating how a device responds to a stimulus. Marker placement can be easily achieved by delaying any given signal. In the prior art, delays are commonly generated in either a ramp delay generator or a gate delayed vernier. In a ramp delay generator, a ramp is triggered by an incoming pulse. A high speed digital-to-analog converter ("DAC") sets a comparator trip point, which is compared to the ramp output. When the ramp output passes the comparator trip point, an output pulse is generated. The delay from the input pulse can thus be made proportional to the programmed DAC voltage, i.e. comparator trip point. Therefore, the higher the trip point setting, the longer the delay from the input pulse.
In a gate delayed vernier, the tapped delay line uses an assortment of gates and multiplexers to set the delay for the incoming pulses. This method recovers very quickly and can be implemented by monolithic construction.
There typically are, however, several disadvantages in the prior art delay generators. For the ramp delay generator, it typically is difficult to make a ramp generator which recovers quickly enough to be retriggered at the rates required for today's high speed ATSs, which typically run at a vector rate of up to 200 MHz. Also, even if a ramp generator can be made to recover quickly, the resulting aberrations typically cause large non-linearities in the delay versus the DAC voltage. Finally, it often is extremely difficult to make a scale factor of delay versus DAC voltage as accurate as required for meshing the vernier with the system clock.
As to the gate delay vernier, the gate delays often vary significantly with process and temperature and therefore must be calibrated in the system. Also, a lookup table typically must be used to convert a programmed delay value to the gate selection since this conversion is non-algorithmic. This table is potentially quite massive and must be accessed at functional speeds of the ATS to be effective.